Table of Contents

Siemens / Vector jump protection _ Setting & highlights _ SI5070

Table of Contents

Overview

The “Vector jump protection” function is used for network decoupling of the power generating unit in case of a load loss, and evaluates the phase-angle jump of the voltage phasors.

For more detailed information on “Vector jump protection” function, refer to SIPROTEC 5 devices, V8.30 & higher manuals.

To see other supported functions click here.


Structure/Embedding of the Function

Structure/Embedding of the Vector jump protection Function

Setting Parameters


General setting parameters

Addr. Parameter C Setting Options Default Setting
General
_:2311:102 General:Threshold V1 min   0.300 V to 175.000 V 46.189 V
_:2311:101 General:Threshold V1 max   0.300 V to 175.000 V 75.058 V
_:2311:6 General:T Block   0.00 s to 60.00 s 0.10 s

Setting parameters for Δφ Stage

Addr. Parameter C Setting Options Default Setting
Stage Δφ 1
_:19261:1 Stage Δφ 1:Mode   off
on
test
off
_:19261:2 Stage Δφ 1:Operate & flt.rec. blocked   no
yes
no
_:19261:101 Stage Δφ 1:Threshold Δφ   2.0° to 30.0° 10.0°
_:19261:6 Stage Δφ 1:Operate delay   0.00 s to 60.00 s 0.00 s
_:19261:7 Stage Δφ 1:T Reset   0.00 s to 60.00 s 5.00 s

Setting parameters for I1 < Release Stage

Addr. Parameter C Setting Options Default Setting
I1 < Release #
_:101 I1 < Release #:I< Threshold 1 A @ 100 Irated 0.030 A to 35.000 A 0.100 A
5 A @ 100 Irated 0.15 A to 175.00 A 0.50 A
1 A @ 50 Irated 0.030 A to 35.000 A 0.100 A
5 A @ 50 Irated 0.15 A to 175.00 A 0.50 A
1 A @ 1.6 Irated 0.001 A to 1.600 A 0.100 A
5 A @ 1.6 Irated 0.005 A to 8.000 A 0.500 A

Logic Diagrams & highlights


Voltage Vector of the Steady State

Voltage Vector of the Steady State

Vector Change after the Load Shedding

Vector Change after the Load Shedding

Vector Description

Vector Description

Logic Diagram of the General Functionality

Logic Diagram of the General Functionality

Logic Diagram of the Δφ Stage

Logic Diagram of the Δφ Stage

Logic Diagram of the I1 < Release Stage

Logic Diagram of the I1 < Release Stage

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