Overview
Shunt Capacitor Banks (SCB) are used in a power system to provide reactive power compensation and power factor correction. They are as well used as integral parts of Static Var Compensators (SVC) or Harmonic Filters installations. The “Capacitor bank protection” function is specially designed to provide protection and supervision features for SCBs.
For more detailed information on “Capacitor bank protection” function, refer to ABB, Relion 670 Series manuals.
To see other supported functions, click here.
Function Identification
| Function description | IEC 61850 identification |
IEC 60617 identification |
ANSI/IEEE C37.2 device number |
| Capacitor bank protection | CBPGAPC | – | – |
Signals & Setting Parameters
CBPGAPC function block
CBPGAPC Input signals
| CBPGAPC Input signals | |||
| Name | Type | Default | Description |
| I3P | GROUP SIGNAL | – | Three Phase Current Input |
| BLOCK | BOOLEAN | 0 | Block the complete function |
| BLKTR | BOOLEAN | 0 | Block all trip output signals |
| BLKOC | BOOLEAN | 0 | Block over current functionality |
| BLKUC | BOOLEAN | 0 | Block under current functionality |
| BLKUCCUT | BOOLEAN | 0 | Block UC function when the capacitor bank is disconnected |
| BLKQOL | BOOLEAN | 0 | Block reactive power over load functionality |
| BLKHOL | BOOLEAN | 0 | Block harmonic over load functionality |
CBPGAPC Output signals
| CBPGAPC Output signals | |||
| Name | Type | Description | |
| TRIP | BOOLEAN | General trip signal | |
| TROC | BOOLEAN | Trip signal for over current | |
| TRUC | BOOLEAN | Trip signal for under current | |
| TRQOL | BOOLEAN | Trip signal for reactive power over load | |
| TRHOL | BOOLEAN | Trip signal for harmonic over load | |
| START | BOOLEAN | General start signal | |
| STOC | BOOLEAN | Start signals for over current | |
| STUC | BOOLEAN | Start signal for under current | |
| STQOL | BOOLEAN | Start signal for reactive power over load | |
| STHOL | BOOLEAN | Start signal for harmonic over load | |
| STOCL1 | BOOLEAN | Start signal for over current of phase L1 | |
| STOCL2 | BOOLEAN | Start signal for over current of phase L2 | |
| STOCL3 | BOOLEAN | Start signal for over current of phase L3 | |
| STUCL1 | BOOLEAN | Start signal for under current of phase L1 | |
| STUCL2 | BOOLEAN | Start signal for under current of phase L2 | |
| STUCL3 | BOOLEAN | Start signal for under current of phase L3 | |
| STQOLL1 | BOOLEAN | Start signal for reactive power over load of phase L1 | |
| STQOLL2 | BOOLEAN | Start signal for reactive power over load of phase L2 | |
| STQOLL3 | BOOLEAN | Start signal for reactive power over load of phase L3 | |
| STHDTL1 | BOOLEAN | Start signal harmonic over load Definite Time stage phase L1 | |
| STHDTL2 | BOOLEAN | Start signal harmonic over load Definite Time stage phase L2 | |
| STHDTL3 | BOOLEAN | Start signal harmonic over load Definite Time stage phase L3 | |
| STHIDML1 | BOOLEAN | Start signal for harmonic over load IDMT stage of phase L1 | |
| STHIDML2 | BOOLEAN | Start signal for harmonic over load IDMT stage of phase L2 | |
| STHIDML3 | BOOLEAN | Start signal for harmonic over load IDMT stage of phase L3 | |
| RECNINH | BOOLEAN | Capacitor bank reconnection inhibit signal | |
CBPGAPC Group settings (basic)
| CBPGAPC Group settings (basic) | |||||
| Name | Values (Range) | Unit | Step | Default | Description |
| Operation | Off On |
– | – | Off | Operation Off/On |
| OperationRecIn | Off On |
– | – | On | Inhibit reconnection for operation Off/On |
| IRecnInhibit< | 4 – 1000 | %IB | 1 | 10 | Current in % of IBase below which the SCB is disconnected |
| tReconnInhibit | 1.00 – 6000.00 | s | 0.01 | 300.00 | Time delay for Capacitor Bank voltage to discharge to <5% |
| OperationOC | Off On |
– | – | On | Operation over current Off/On |
| IOC> | 10 – 900 | %IB | 1 | 135 | Start level for over current
operation, % of IBase |
| tOC | 0.00 – 6000.00 | s | 0.01 | 30.00 | Time delay for over current operation |
| OperationUC | Off On |
– | – | Off | Operation under current Off/On |
| IUC< | 5 – 100 | %IB | 1 | 70 | Start level for under current operation in % of IBase |
| tUC | 0.00 – 6000.00 | s | 0.01 | 5.00 | Time delay for under current operation |
| OperationQOL | Off On |
– | – | On | Operation reactive power over load Off/On |
| QOL> | 10 – 900 | % | 1 | 130 | Start level for reactive power over load in % |
| tQOL | 1.00 – 6000.00 | s | 0.01 | 60.00 | Time delay for reactive power overload operation |
| OperationHOL | Off On |
– | – | On | Operation harmonic over load Off/On |
| HOLDTU> | 10 – 500 | % | 1 | 200 | Start value of voltage in % for DT harmonic voltage overload |
| tHOLDT | 0.00 – 6000.00 | s | 0.01 | 10.00 | Time delay for operation of harmonic voltage overload |
| HOLIDMTU> | 80 – 200 | % | 1 | 110 | Start value of voltage in % for IDMT harm. voltage overload |
| kHOLIDMT | 0.50 – 1.50 | – | 0.01 | 1.00 | Time multiplier for harmonic voltage overload IDMT curve |
| tMaxHOLIDMT | 0.05 – 6000.00 | s | 0.01 | 2000.00 | Maximum trip delay for harmonic voltage overload |
| tMinHOLIDMT | 0.05 – 60.00 | s | 0.01 | 0.10 | Minimum trip delay for harmonic voltage overload |
CBPGAPC Non group settings (basic)
| CBPGAPC Non group settings (basic) | |||||
| Name | Values (Range) | Unit | Step | Default | Description |
| GlobalBaseSel | 1 – 12 | – | 1 | 1 | Selection of one of the Global Base Value groups |
CBPGAPC Monitored data
| CBPGAPC Monitored data | ||||
| Name | Type | Values (Range) | Unit | Description |
| IPEAKL1 | REAL | – | A | Equivalant RMS current for phase L1 |
| IPEAKL2 | REAL | – | A | Equivalant RMS current for phase L2 |
| IPEAKL3 | REAL | – | A | Equivalant RMS current for phase L3 |
| URMSL1 | REAL | – | % | Calculated voltage RMS for phase L1 |
| URMSL2 | REAL | – | % | Calculated voltage RMS for phase L2 |
| URMSL3 | REAL | – | % | Calculated voltage RMS for phase L3 |
| QL1 | REAL | – | % | Reactive power value for phase L1 |
| QL2 | REAL | – | % | Reactive power value for phase L2 |
| QL3 | REAL | – | % | Reactive power value for phase L3 |
Logics & highlights
Quantities formula (1/2)
Quantities formula (2/2)
Simplified logic diagram about used analog quantities within one phase
Capacitor bank energization check for one phase. Similar for all three phases
Capacitor bank reconnection inhibit
Capacitor bank overcurrent protection
Capacitor bank undercurrent protection
IDMT curve for harmonic overload (kHOLIDMT=1.0)
Simplified logic diagram for harmonic overload
Capacitor bank reactive power overload protection
