Overview
According to IEEE standard C37.100 entitled IEEE Standard Definitions for Power Switchgear, restrike is defined as “a resumption of current between the contacts of a switching device during an opening operation after an interval of zero current of ¼ cycle at normal frequency or longer.” The “Breaker restrike” algorithm responds to a successful interruption of the phase current following a declaration of capacitor bank offline as per the breaker pole indication.
For more detailed information on “Breaker restrike” element, refer to GE, Universal Relay (UR) family of products, Version 8.0x manuals.
To see other supported elements, click here.
Setting Parameters
Modbus memory map for Setting parameters
| Products | Hex address | Register name | Range | Units | Step | Format | Default |
| B30, C60, C70, C95, D60, F35, F60, G60, L60, L90, M60, T60 | 6371 | Breaker Restrike 1 Function | 0 to 1 | — | 1 | F102 | 0 (Disabled) |
| " | 6372 | Breaker Restrike 1 Block | 0 to 4294967295 | — | 1 | F300 | 0 |
| " | 6374 | Breaker Restrike 1 Signal Source | 0 to 5 | — | 1 | F167 | 0 (SRC 1) |
| " | 6375 | Breaker Restrike 1 Pickup | 0.1 to 2 | pu | 0.01 | F001 | 50 |
| " | 6376 | Breaker Restrike 1 Reset Delay | 0 to 65.535 | s | 0.001 | F001 | 100 |
| " | 6377 | Breaker Restrike 1 HF Detect | 0 to 1 | — | 1 | F102 | 1 (Enabled) |
| " | 6378 | Breaker Restrike 1 Breaker Open | 0 to 4294967295 | — | 1 | F300 | 0 |
| " | 637A | Breaker Restrike 1 Open Command | 0 to 4294967295 | — | 1 | F300 | 0 |
| " | 637C | Breaker Restrike 1 Close Command | 0 to 4294967295 | — | 1 | F300 | 0 |
| " | 637E | Breaker Restrike 1 Target | 0 to 2 | — | 1 | F109 | 0 (Self-reset) |
| " | 637F | Breaker Restrike 1 Events | 0 to 1 | — | 1 | F102 | 0 (Disabled) |
| " | 6380 | Reserved (2 items) | — | — | — | F002 | 0 |
| " | 6382 | …Repeated for Breaker Restrike 2 | |||||
| B30, C60, C70, C95, F35, F60, T60 | 6382 | …Repeated for Breaker Restrike 3 |
| F102 | 0 = Disabled, 1 = Enabled | ||||||
| F109 | 0 = Self-reset, 1 = Latched, 2 = Disabled | ||||||
| F167 | 0 = SRC 1, 1 = SRC 2, 2 = SRC 3, 3 = SRC 4, 4 = SRC 5, 5 = SRC 6 | ||||||
Logics & highlights
Typical restrike waveform and detection flag
Algorithm illustration of state machine to detect restrike
Breaker restrike logic
